1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device and, more particularly, to a fabrication method for processing circuits on two opposing planar surfaces of a semiconductor wafer.
2. Description of the Related Art
A conventional integrated circuit generally includes a support substrate and an element layer formed upon the support substrate. The element layer includes various P-type and N-type doped regions which combine to form active transistor devices. Collector or drain terminals of vertical transistors are brought through buried silicon leadout regions to form ohmic contacts at the surface of the element layer. Electrical isolation between these devices is furnished by various forms of isolation barriers. Conventional techniques for forming collector or drain leadouts and isolation regions significantly decrease integrated circuit capabilities and greatly escalate circuit manufacturing costs.
Transistor performance characteristics are determined by the concentration of ions in the doped regions. For example, performance of vertical transistors is improved by reducing collector or drain leadout resistance since elevated resistance levels degrade output voltage swing and frequency response, waste energy through internal dissipation, and raise the temperature of the device thereby reducing reliability and capacity. To reduce the lateral component of collector or drain leadout resistance, a vertical transistor may incorporate a lightly doped collector or drain region overlying a more heavily doped same-type buried layer region. To reduce the vertical component of collector or drain leadout resistance, a heavily doped plug may be diffused into a surface region and buried beneath a surface collector or drain ohmic region.
Thus it is apparently desirable to reduce collector or drain lateral leadout resistance as much as possible by doping the buried layer very heavily. However, in a bipolar transistor for example, the maximum collector-to-emitter voltage is determined by the resistivity and thickness of the active collector region between the base and buried layer. Various high temperature processing steps subsequent to doping of the buried layer expands the buried layer by gas phase and solid state diffusion in proportion to the doping level. Heavy doping of the buried layer decreases the width of the active collector region, reducing transistor voltage capability. To increase the transistor voltage capability of a circuit, element layer thickness cannot be increased without limit because the costs of isolating circuit components becomes prohibitive and leadout resistance increases. Voltage and current capability of integrated vertical devices is thus constrained by these factors.
A strategy for reducing collector or drain leadout resistance is sought which does not require heavy doping of the buried layer or the usage of diffused plugs. In one exemplary process, two silicon wafers are bonded using high temperature bonding in which one of the wafers is previously etched and filled with a low resistivity metal or silicide to form a conductive layer. Numerous difficulties arise in the practice of this process. The silicon layer and conductive layer generally have mismatched thermal coefficients of expansion so that the sustained high temperatures to which the layers are subjected during bonding and subsequent processing cause stresses that result in junction leakage. In addition, the sustained high temperatures cause diffusion of metallic impurities, for example, from the conductive layer into the silicon layer, resulting in reduced minority carrier lifetime and junction leakage.